1. Field of the Invention
The present invention relates to a method for selecting reference images, a method and an apparatus for inspecting patterns on wafers, and a method for dividing a wafer into application regions, and more particularly to a method for selecting a plurality of reference images which may be used to perform pattern inspections in application regions on wafers which correspond to the reference images.
2. Description of the Related Art
In a conventional apparatus for inspecting the appearance of semiconductor integrated devices, once the images of two adjacent semiconductor devices or dies are obtained, the images of the dies are compared to each other by a pixel unit. To determine if one of the dies is defective, the images of the dies are compared. If the images are consistent with each other, the dies are not defective. Such a conventional apparatus may employ an image-capturing device such as a combination of an optical microscope and a time delay integration (TDI) image pickup element to obtain the image. After the image-capturing device scans a first die that may be defective, e.g., in a row direction, the image-capturing device obtains a multi-valued image of the first die. The image-capturing device then stores the image in an image memory device. Next, the image-capturing device takes a multi-valued image of a second die, e.g., a reference die adjacent to the first die, and the image-capturing device stores the image in an image memory. The inspection apparatus reads the images and compares the gray levels of related pixels with each other. A pixel that provides a gray level difference above a threshold value with respect to a related pixel of the reference image is determined to be defective.
Recently, however, sensitivity requirements for appearance inspections have increased due to the design rules for semiconductor devices. In order to improve the defect detecting sensitivity of conventional inspection apparatuses, semiconductor devices to be inspected may exhibit less color unevenness or process noise, such as metal grain, which may be caused by surface irregularities, e.g., metal wiring. In practice, however, it is difficult to reduce process noise from semiconductor devices. Portions of a semiconductor device that have numerous metal grains scatter light, thereby reducing the amount of light entering into an object lens of a microscope and lowering the gray level of the portion corresponding to the image picked up from the semiconductor device. If a fixed threshold is applied to a region when checking the difference between the gray levels of two pixels and process noise is present, the process noise may be recognized as a defect, thereby lowering the defect detecting sensitivity. Thus, since the process noise may be a minor defect, the process noise may not be detected.
To solve these problems, researches have set higher thresholds for brighter regions where metal wires are present, and lower thresholds for dark regions between the metal wires. Therefore, process noise such as the metal grain in the metal wires may not be detected as defects, and defects such as a short between circuit wires may be detected.
FIG. 1 is a flow chart showing a conventional inspection method disclosed in U.S. Pat. No. 6,229,331. Referring to FIG. 1, images are obtained from two dies and stored in an image memory device. Next, group operators are calculated and pixels are divided into groups. After the thresholds for the groups are set, defects are detected by comparing the differences in gray levels to the thresholds.
FIG. 2 depicts a flow chart of a conventional inspection method according to U.S. Pat. Ser. No. 2001/0055415. Referring to FIG. 2, design data is developed and stored to generate reference data. A pattern width for the reference data is then calculated. An actual image is generated by scanning an inspected pattern. Next, an edge existence threshold is calculated from the actual image. A pattern width for the actual image is calculated by searching for a pattern edge position. A reference image is then prepared using a resize width that is calculated for the actual image. Finally, a pattern inspection is performed using the reference image.
FIG. 3 is a schematic diagram illustrating a conventional inspection apparatus according to Japanese Laid Open Patent Publication No. 10-135287. Referring to FIG. 3, the wafer inspecting apparatus includes a means for photographing images of a wafer, a means for contouring the images, a means for measuring the gray levels of the contoured images, and a means for comparing the gray levels of the images.
FIG. 4 is a flow chart showing a conventional inspection method disclosed in Japanese Laid Open Patent Publication No. 2001-133418. As shown in FIG. 4, a test image and a reference image are obtained from an object and aligned. Next, a two-dimensional dispersion map is prepared by plotting the gray levels of the test image and the reference image. The two-dimensional dispersion map is then filtered to reduce noise, and the dispersion map is divided into mask forms. Finally, a defective pixel is discovered by comparing the gray level of the pixel with the gray level of the mask.
However, the apparatus and method described in FIGS. 3 and 4 respectively select one die among the numerous dies located on a wafer. After an image is obtained from the selected die, the image is stored on inspection equipment as a reference image. A pattern inspection is then performed on the entire wafer using the one reference image.
FIG. 5 is a top plan view of a wafer that includes a plurality of semiconductor dies, with one die selected as a reference image according to a conventional method. Referring to FIG. 5, the image of one die (shown with hatched lines in FIG. 5) located at a central portion of a wafer is selected as the reference image. A pattern inspection is then performed on all of the dies of the wafer using the one reference image. However, such a method for inspecting patterns may cause errors with respect to the determination of which dies are truly defective. To identify these identification errors, a sample wafer manufactured under a design rule of 0.11 μm may be provided, and then etched back. The gray level of a die located at the central portion of the sample wafer and the gray level of a die located at the edge portion of the sample wafer may then be measured.
Referring to FIG. 6, which is a histogram illustrating the gray levels of the central die of the wafer depicted in FIG. 5, the gray level of the central die is distributed between approximately 80 and 140. FIG. 7 is a histogram depicting the gray level of an edge die of the wafer depicted in FIG. 5. As shown in FIG. 7, the gray level of the edge die is approximately 255. As can be seen by comparing FIGS. 6 and 7, the gray level of the central die and the gray level of the edge die are remarkably different from each other.
FIG. 8 is a photograph of the wafer depicted in FIG. 5 in which a pattern inspection has been performed on all of the dies using the image of a center die as the reference image. As shown in FIG. 8, most dies located at the central portion of the sample wafer are shown as not being defective, and most dies located at the edge portion of the wafer are shown as being defective. Thus, because of the difference in the gray levels of the central dies and the edge dies, edge dies having no defects may be improperly identified as defective dies.
On the other hand, referring to FIG. 9, which is a photograph of the wafer depicted in FIG. 5 in which a pattern inspection has been performed on all of the dies using the image of an edge die as the reference image, most of the edge dies are shown as not being defective while most central dies, which do not have defects, are shown as being defective.
Therefore, errors with respect to the determination of defective dies may occur when one image of a central die or on image of an edge die is used as the reference image and a pattern inspection is performed on all of the dies of the wafer.